While Xillybus' main focus is data transport over PCIe, this is not always the optimal solution for certain designs. In particular, USB is often preferred for hardware that is external to the computer. Also, for low-cost devices, the FPGA devices equipped with PCIe infrastructure may have a significant impact on the overall BOM.

Xillybus over USB is planned for design and release during 2019. The API on the FPGA side will be exactly the same as the current IP cores, with a plain FIFO interaction. This will allow a smooth transition from FPGA designs based upon Xillybus over PCIe to Xillybus over USB.

Some implementation details are yet to be established, however the IP core will cover only USB 3.0, without a fallback option to USB 2.0. This means that the host's port must be USB 3.0 compliant, or no communication takes place at all.

The host API is planned to remain the same as well, with a difference in how the driver is deployed: Rather than a kernel driver, Xillybus over USB will be accessed through a user-space program running as a daemon (or service on Windows), based upon libusb. This is the case for both Linux and Windows. This simplifies the deployment of software based upon Xillybus over USB. From the application software's point of view, the difference is only that instead of opening a device file, a named pipe is accessed.

In practice, this only means changing the path to the file opened from e.g. /dev/xillybus_read_32 to /tmp/xillybus_read_32. Or in Windows, from \\.\xillybus_read_32 to \\.\pipe\xillybus_read_32. Other than this, the named pipe will behave exactly the same as the device files related to Xillybus over PCIe / AXI.

Comments and other inquiries on this matter are welcome.