Illustration of Xillybus principle

A simple turnkey solution

  • Xillybus consists of an FPGA IP core and a driver for the computer: All the low-level design is already done. Read more...
  • FPGA designers interface with the IP core through a standard FIFO or dual-port memory
  • Computer software programmers work in userspace with files, following classic UNIX programming style
  • Works intuitively on both sides
  • True streaming feel, no need to manage buffers. Any amount of data dropped on one side appears on the other.
  • No complicated API to learn on either side.
  • No driver programming
  • Based upon PCI Express or AXI bus
  • No PCI Express or other bus development
  • Runs out-of-the-box on Windows 7 and recent Linux distributions

Features

  • Very fast setup: A day or two is the typical lead time from downloading core & drivers to an end-to-end integration between host application and dedicated logic on FPGA.
  • Try it first: Get your own custom built IP core for evaluation, and test it in your real design.
  • Portability: Seamless transition between Xilinx and Altera, Linux and Windows
  • Robust pipe communication stream that just works.
  • Scalable and flexible: Up to 160 FIFOs sharing a single PCIe link.
  • Cuts development risk, cost and schedule dramatically
  • Straightforward use for designers
  • DMA used exclusively for data transfers, hence minimal load on processor.
  • Low latency
  • Intuitive data flow in both ends
  • Custom generation of core to meet client's needs

Applications

  • Data acquisition
  • HPC (High Performance Computing)
  • FPGA control from host
  • Easy design of peripherals
  • Interface with dedicated hardware
  • Logic verification on hardware
  • Fast development of dedicated lab equipment
  • Debugging (Chipscope on steroids)
  • Data interchange with High Level Synthesis (HLS) function

Host platforms

  • Anything with PCIe: Common PC computers, PC-on-board (PCI/104-Express) and embedded processors (e.g. i.MX 6)
  • Xilinx' Zynq-7000 EPP
  • Altera Cyclone V SoC
  • Microblaze soft processor with AXI4 bus

Download


Download a kit!
Try Xillybus with your application data from the FPGA to the host and vice versa. It's not just a demo, it works for real. Connect your application data to a standard FIFO, boot the computer or FPGA with either Windows or Linux, and see how easy it is to talk with your FPGA!

Click here for more about how Xillybus works.