While migrating the Xillybus general-purpose DMA stream IP Core to Virtex-7 devices supporting Gen3 PCI, it turned out that Xilinx’ PCIe block’s interface has changed dramatically.

Virtex-7 devices in the XT/HT group (except for 485T) are equipped with a PCIe core supporting the PCIe 3.0 standard, commonly referred to as the Gen3 Integrated Block for PCIe. This core is the only PCIe block available on these devices, regardless of the required standard level or bandwidth. This is why the Coregen refuses the choice of the 7-series core for PCIe with XT/HT devices.

Compared with previous PCIe cores available with Coregen, the Gen3 Integrated Block presents fundamental differences in its interface and data flow. Migrating an existing design using PCIe on previous Xilinx devices goes far beyond some minor technical modifications, and involves redesigning some of the application logic.

Having said that, the overall impression is that the Gen3 PCIe block was designed to be user friendly. The rationale behind many of the changes is obviously minimizing the chances to get things wrong. Other changes make sense from a plain engineering point of view.

It’s important to realize, that the incompatibilities are not a result of some new wrapper logic generated by coregen. There is a PCIE_3_0 logic primitive for the PCI functionality, to which most of the signals of the core are connected directly (in particular, the AXI4 Stream signals). Once these XT/HT devices are out, there is little one can do to return the wheel back.

This is a short summary of the key issues that need to be dealt with, when migrating a PCIe-enabled design to Virtex-7 XT/HT devices (again, 485T counted out), for the sake of retaining Gen1/2 functionality. This is by no means an attempt to cover all aspects of the migration. There is no substitute to reading the user guide carefully.

This Howto should be considered a work in progress, and not an authoritative source. It's based upon the Virtex-7 FPGA Gen3 Integrated Block for PCI Express v2.1 (pg023) guide and some hands-on experience with the core's version 1.6, under ISE 14.6 during September 2013.


This is a brief listing of the main issues to be aware of. They are detailed further in the following parts.

  • Two pairs of AXI Stream interfaces with different functions, rather than a single pair.
  • The payload is represented in little Endian order (as opposed to big Endian in the TLPs).
  • The TLP headers are abandoned, and replaced with a dedicated descriptor format which is used for communication with the Gen3 Block.
  • Packets from the application logic to the Gen3 Block must be sent continuously. The application may not drop the “valid” signal in the middle of a packet.
  • Extra logic is required to deliver interrupts reliably: Interrupt requests may fail or arrive out of order w.r.t. transmitted data packets, unless application logic ensures correct operation.
  • The application logic doesn’t know (and doesn’t need to know) its bus ID (bus / device / function numbers): The Requester / Completer ID is inserted into the transmitted TLPs by the Integrated Block.
  • Message TLPs are received on a separate interface (not on either of the AXI-Stream interfaces)

Two physical functions (PF0 and PF1) are supported. Virtual Channels are supported as well. Both of these features are unnecessary in virtually any design that was migrated from older PCIe cores. They add a lot of noise to product guide and to the interfaces with the Block nevertheless. The recommended practice is not to enable PF1 nor virtual channels, and ignore any reference to these. And select PF0 where applicable.

A more detailed outline of the migration issues is given in the next parts.

Comments and corrections are warmly welcomed in the Xillybus forum. Posting is possibly anonymous.

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