Want to avoid Verilog / VHDL coding? Consider the Block Design Flow.

General notes

This last part is dedicated to completing the picture with a few topics having no particular relation to each other.

Global variables

Global variables and static variables within functions behave in synthesized code just like C/C++ code compiled for a processor.

When using Xillybus together with HLS, it’s however required that any global variable is defined static. In other words, these global variables are accessible only within the certain C/C++ file. The reason is that the “expose_global” flag is enabled for the entire project, meaning that any non-static global variable is turned into an I/O port in the logic level, so that variable can be interfaced directly with Verilog code. This feature is used by the debug functions.

Defining non-static global variables in any of the source files consumed by the HLS compiler may lead to unnecessary use of logic resources of the FPGA, failure to implementing the project in Vivado and possibly unpredictable behavior of the variable itself.

If non-static variables must be used, the expose_global flag must be turned off. Also, the debug-related source must be removed from the project, as well as their reference in xillydemo.v. The debug functions will not be available under this condition, of course.

Logic reset

The logic, which is generated by HLS, is held in a reset state when either /dev/xillybus_read_32 and/or /dev/xillybus_write_32 files is unopened by the host. By default, this resets the execution of any synthesized C/C++ code and also the communication with the host. In other words, if a host application is terminated (hence closing the Xillybus files) and then run again, it’s guaranteed that the synthesized code starts from the beginning, and that the data pipes start from fresh. In particular, if there was an unintentional mismatch between the expected number of words for transmission, this is cleared up when these files are closed and opened again.

On the other hand, static variables are not cleared to their initial values, and neither are global variables and arrays of data if such are defined.

If a broader reset behavior is desired, this can be changed as described in Xilinx’ High-Level Synthesis Guide.

The HLS project’s setup

The HLS project in the sample code bundle was set up with the default parameters, with the following configuration:

The following line was added to script.tcl (originally in directives.tcl, but HLS moved it):

config_interface -all ap_fifo -expose_global

This is necessary for the debug utilities to work (and is also the reason why any user-defined global variable must be static, or it’s exposed as a Verilog port too). The meaning of this setting is detailed in HLS' user guide.