This temporary preview release is deprecated.
Unless you're using the temporary version, information on this page is irrelevant and confusing.
Please refer to Xillinux' main page for a proper kit for ZyBo.
This release is now phased out, with the arrival of Xillinux-1.3, which supports ZyBo better. This page is left for those who already have the temporary version installed, and don't wish to upgrade.
This early revision is an adaption of Zedboard's existing Xillinux distribution, with minimal changes made to run properly on ZyBo. As a preview release, early availability was preferred over cleaning up quirks.
The immediate differences are:
- The board's sound is not supported (yet). More precisely, Linux behaves as if sound is supported, but no sound is heard nor captured.
- ZyBo has less fewer LEDs, buttons etc. An attempt has been made to retain a common-sense compatibility, but obviously some functionality is lost.
- Some work flows are slightly different from Zedboard, as detailed below.
Downloading the bundle for ZyBo
Xillinux for Zybo is based upon the same SD card image as Xillinux-1.1 for Zedboard. The PL (FPGA) part bundle is different however.
You need to download the two following items.
- Click here to download the boot files creation kit for Xilinx' tools.
- Click here to download the SD card image.
Mandatory: Replacing files in the SD image
After the SD card image has been copied to the microSD card, a file replacement needs to be done:
- Delete the two files in the SD card's FAT partition: devicetree.dtb and zImage. Recall that this partition is ~16 MB, and is detected by Windows computers as well as Linux.
- Copy all files in the FPGA bundle's boot/ subdirectory (boot.bin, devicetree.dtb, zImage) into the FAT partition (instead of those just deleted)
Important: Even though the old devicetree.dtb and zImage files may appear similar, their replacement as described above is mandatory, or booting Linux will fail with peculiar errors. In particular, the new zImage has an extra patch applied to cope with the lack of a write-protection pin on ZyBo's SD card interface. Even though the zImages present the same Linux version, the previous will refuse to mount the root filesystem, thinking it's write protected.
Changes in the PL (FPGA) build flow
The build process is exactly the one described for Zedboard in the previous version of Getting started with Xillinux for Zynq-7000 EPP (with ISE version 14.2 and up), except that the boot.bin file should not be generated as described in section 3.6. As a matter of fact, this bundle's boot/ subdirectory doesn't have the files necessary to carry this out.
Instead of building boot.bin from several files in the boot/ directory, xillydemo.bit (alone) is converted into xillydemo.bin, and copied into the FAT partition in BIN format. This step is eliminated in Xillinux-1.3.
In order to make this conversion, navigate with a shell prompt to the directory containing xillydemo.bit, and type
promgen -w -b -p bin -o xillydemo.bin -u 0 xillydemo.bit -data_width 32
A shell prompt having promgen in its execution path can be launched from XPS, by picking Project > Launch Xilinx Shell.
Then copy xillydemo.bin into the FAT partition. Note that it's the BIN file,
and not the BIT file.
Using the IP core factory with ZyBo
To work with the temporary version, custom IP cores for ZyBo are built as if they were intended for "old Zedboard". There is no functional difference.
Some extra manual editing is however necessary when installing a custom IP core that was intended for Zedboard, to handle differences in the VGA signal widths. Failing to do this will cause the VGA screen to appear darker and discolored, but has no other effect.
- The README file in the custom IP core bundle says that the existing xillybus.v file should be overwritten with the one that arrives with the bundle, which is incorrect for ZyBo. Instead, the old and new file should be manually merged, so that Verilog code that the signal vector widths of vga4_* signals remains untouched. The vectorized instantiation of vga_iob_ff should remain [17:0], and not reduced to [13:0].
- If the template file for VHDL in the custom core bundle (template.vhd) is referred to, the component declaration for the "xillybus" module states incorrect vector widths for vga4_* signals.