Error message

xillybus: Failed to obtain IDT. Aborting.


This fatal error message is issued as a result of failing to obtain metainformation from the FPGA. This condition is never expected to happen, and most likely indicates unreliable hardware (e.g. FPGA timing constraints set up improperly).

The relevant error condition occurs only after a previous successful transaction of other metadata from the FPGA, so this is a clear case of quirky behavior.

Recommended action

This is most likely not an issue with the Xillybus core itself, but may very well be related to improper timing constraining or a poor system clock. The FPGA should be checked for causes of unreliable operation.

Normal operation may be achieved by unloading and reloading the Xillybus kernel module.