Error message

xillybus: Timed out while flushing. Output data may be lost.


This warning indicates that data, which was written to a Xillybus device file, most likely never reached its destination at the FPGA.

This condition is a result of user application logic on the FPGA holding the "full" signal asserted for a significant period of time, preventing the transmission of data through the interface. When a device file is closed, the driver attempts to send any remaining data before closing ("flushing"), but will timeout after one second if the FPGA doesn't accept the data. The warning above is issued only if some data was left for transmission when the file was closed.

Another possibility for this warning is that the total size of the DMA buffers is larger than what the FPGA drains during a second. If the program attempts to close the file descriptor immediately after the last piece of data has been written to it (which is what most programs do), the data in the DMA buffer will not have a chance to drain within that second, and the remaining data is lost due to a forced close.

In theory, the driver could have waited indefinitely for a complete data transmission before closing the file, but since file closing is part of process termination, an FPGA interface refusing to accept data could prevent the cleanup of a defunct process, had it not been for the timeout.

Recommended action

In most cases, this warning can be ignored, in particular when it appears in conjunction with killing processes with CTRL-C or with some other signal.

When it's mandatory for all written data to reach the FPGA, the FPGA application logic should be modified not to stall the data flow for as long as a second, or the size of the DMA buffers can be reduced to less than a second's worth of data (with a custom IP core). It's also possible to force the flush of the buffers before closing the file descriptor with no time limit, by issuing a zero-length write() call.