Error message information

This fatal error indicates that meta information sent from FPGA to host arrived with invalid content. This condition is never expected to happen, and most likely indicates unreliable hardware (e.g. FPGA timing constraints set up improperly).

If this error appears in conjunction with other fatal errors, they may give the reason.

This is most likely not an issue with the Xillybus core itself, but may very well be related to improper timing constraining or a poor system clock. The FPGA should be checked for causes of unreliable operation.

Normal operation may be achieved by unloading and reloading the Xillybus kernel module.