|My saved IP cores|
IP core's nameThe IP core's name is given for your own reference. Except for appearing in this site and in the "readme" file going along with the delivered IP core, it has no significance. In particular, it has no effect on the logic generated.
The name consists of English letters and possibly underscores. Other characters or white spaces are not allowed. The first character must be a letter. The maximal length is 24 characters.
Operating systemThere are slight differences in the performance possibilities when the IP core runs under Windows or Linux.
Including an operating system which is never used may cause an unnecessary performance hit due to irrelevant restrictions on the IP core's settings.
On the other hand, not including a targeted operating system can cause a failure to load the driver on the host.
Target device familyThe IP core is delivered as a netlist, which must match the target device family for proper inclusion in a project.
Those targeting Zedboard with Xillinux-1.1 should pick "Old Zedboard". Just "Zedboard" stands for the current version, Xillinux-1.3. More information on this page.
Virtex-7 XT and HT (except 7VX485T) have a Gen3 PCIe block. For all other Virtex-7 FPGA, pick Gen2.
If you need a target that isn't listed here, it may be available as a Beta version. Please issue a request through email.
Initial templatePick "Demo bundle setting" for starting the custom IP core with the device files that are included in the demo bundle. This is recommended when using this tool for the first time.
Alternatively, pick "Empty" to start from scratch.