Download the demo bundle
IMPORTANT: The Xillybus IP core in the demo bundle is configured for simplicity rather than performance. Significantly better results can be achieved for applications requiring a sustained and continuous data flow, in particular for high-bandwidth cases. It's therefore recommended to build your own custom IP core after finishing the flow with the demo bundle.
You need to download two items, one from each of the two bundle groups below (or the FPGA bundle only, if certain Linux distributions are chosen). Please refer to the "getting started" guides in the documentation page afterwards.
The FPGA bundle:
The following table lists the boards for which an out-of-the box demo bundle is available.
|Xilinx||Virtex-5||1x||~ 200 MB/s||ML506||Click to download|
|Spartan-6||1x||~ 200 MB/s||SP605||Click to download|
|Virtex-6||4x||~ 400 MB/s||ML605||Click to download|
|Kintex-7||8x||~ 800 MB/s - 3.5 GB/s(***)||KC705||Click to download|
|Virtex-7 w/ Gen2(*)||8x||~ 800 MB/s - 3.5 GB/s(***)||VC707||Click to download|
|Virtex-7 w/ Gen3(*)||8x||~ 800 MB/s - 3.5 GB/s(***)||VC709||Click to download|
|Artix-7||4x||~ 400 MB/s - 1.6 GB/s(***)||AC701||Click to download|
|Kintex Ultrascale||8x||~ 800 MB/s - 3.5 GB/s(***)||KCU105||Click to download|
|Virtex Ultrascale||8x||~ 800 MB/s - 3.5 GB/s(***)||VCU108||Click to download|
|Zynq-7000 (PCIe)||4x||~ 800 MB/s - 3.5 GB/s(***)||ZC706||Available upon request|
|Zynq-7000 (PL/PS interface)||N/A||~ 300 MB/s||Zedboard, ZyBo and MicroZed||Please refer to Xillinux' page|
|Altera||Cyclone IV||1x||~ 200 MB/s||Cyclone IV Transceiver starter kit||Click to download|
|4x||~ 400 MB/s||Cyclone IV GX FPGA development kit||Click to download|
|Stratix IV||4x||~ 400 MB/s||Terasic DE4||Click to download|
|4x||~ 400 MB/s||Stratix IV GX FPGA Development Kit||Click to download|
|Arria II||4x||~ 400 MB/s||Arria II GX FPGA Development Kit||Click to download|
|Cyclone V||4x||~ 400 MB/s - 1.6 GB/s(***)||Cyclone V GT FPGA Development Kit||Click to download|
|Arria V||4x||~ 400 MB/s - 1.6 GB/s(***)||Arria V GX FPGA Development kit||Click to download|
|4x||~ 400 MB/s - 1.6 GB/s(***)||Arria V GX FPGA Starter Kit||Click to download|
|Stratix V||4x||~ 800 MB/s - 3.5 GB/s(***)||Stratix V GX FPGA Development Kit||Click to download|
|4x||~ 800 MB/s - 3.5 GB/s(***)||Stratix V DSP Development Kit||Click to download|
|Arria 10||8x||~ 800 MB/s - 3.5 GB/s(***)||Arria 10 GX FPGA Development Kit||Available upon request|
|Cyclone V SoC||N/A||~ 200 MB/s||SoCKit board||Please refer to Xillinux' page|
(*) For Virtex-7 XT and HT (except 7VX485T), pick the bundle for Gen3. For all other Virtex-7 FPGA, the Gen2 bundle.
(**) Please refer to this page for best practices on achieving the desired bandwidth. For information about the bandwidth limits, please refer to this page. There's also a page about latency.
(***) Revision B/XL cores with data rates up to 3.5 GB/s are available for selected devices upon request. Click here to read more.
Code bundle for the host:
Xillybus works out of the box with certain Linux distribtions, e.g. Ubuntu 14.04 and later. Also, Xillybus' driver is included in Linux kernel sources from 3.12.0 and later (but is not included in all precompiled kernels and module sets).
- Click here to download the driver for Windows 7 (32/64 bit).
- Click here to download the Linux driver, udev file, sample C applications and the diagnostic utility. If a kernel older than 2.6.36 is targeted, an older version of the Linux package is available upon request, but it's likely to be outdated with respect to the IP cores.
- The Xillybus package for Windows is recommended for testing Xillybus on a Windows host.