1 Introduction
1.1 General
1.2 How to integrate the custom IP core
2 Defining custom IP cores
2.1 Overview
2.2 The device file’s name
2.3 Data width
2.4 Use
2.5 Synchronous or asynchronous stream
2.6 Buffering time
2.7 Size of DMA buffers
2.8 DMA acceleration
3 Scalability and logic resource consumption
3.1 General
3.2 Block RAMs
3.3 Resources of logic fabric
4 IP cores of revisions B, XL and XXL
4.1 General
4.2 Working with revision B/XL/XXL
4.3 Width of data word
4.4 Logic resource consumption
4.5 Tuning for optimal bandwidth of stream from host to FPGA
