1 Introduction
2 General guidelines
2.1 Clocking
2.2 Data width
2.3 Interfacing through a FIFO
2.4 Behavior of “empty” and “full” signals
3 Description of signals
3.1 Naming convention of FPGA signals
3.2 Signals for host to FPGA transmission
3.3 Signals for FPGA to host transmission
3.4 Memory interface signals
3.5 The quiesce signal
4 Implementing data acquisition
4.1 Introduction
4.2 Example code
4.3 FIFO connections
4.4 Data acquisition control
4.5 Generating EOF
4.6 A test run
4.7 Monitoring the amount of buffered data
5 Suggested methods for simulation
5.1 General
5.2 Simulating asynchronous streams
5.3 Simulating synchronous streams
5.4 A simplified method for simulation
