1 Introduction
Xillybus’ IP cores are intended to interface with user application logic through a FIFO or a dual-port block RAM. Therefore, it is usually possible to work with the IP core without understanding the API in detail.
The vast majority of the API’s rules can be deduced from a simple principle: The user application logic should behave exactly like a FIFO or a block RAM. This is true even when the application logic interfaces with the IP core directly.
Among others, this principle means that the exchange of data between the Xillybus IP core and the user application logic takes place at a pace that is dictated by the IP core. The data flow may stop momentarily and resume later in an unpredictable manner. In other situations, the data flow will be continuous. This poses no problem when the IP core is connected directly to a FIFO or a block RAM. Likewise, user application logic that interfaces directly with the IP core should also operate properly even when the data flow starts and stops in an unpredictable manner.
It’s a common mistake to consider the IP core’s irregular access pattern as a bug. Unexplainable pauses in the data flow between the IP core and the FIFO may seem suspicious, but they don’t indicate any malfunction.
It’s not recommended to interface with the IP core directly (i.e. without a FIFO or block RAMs) in order to reduce the logic consumption. This holds true in particular in the early stages of the design. If the user application logic is connected directly to the IP core, the irregular data flow may expose bugs in the application logic.
This guide describes the API that is relevant for interfacing application logic directly, and also elaborates on popular applications.
It’s recommended to gain an initial experience with Xillybus before delving into the details that are presented in this guide. Refer to these documents:
This guide also assumes that you understand the difference between synchronous and asynchronous streams. This is discussed in section 2 of either of these two documents:
XillyUSB IP cores expose the same API, and are a subset of Xillybus IP cores. Accordingly, the name “Xillybus” refers to XillyUSB IP cores as well in this guide, unless said otherwise.
For those who are curious, a brief explanation on how Xillybus is implemented can be found in Appendix A of either Xillybus host application programming guide for Linux or Xillybus host application programming guide for Windows.