1 Introduction
2 Prerequisites
2.1 Hardware
2.2 FPGA project
2.3 Development software
2.4 Experience with FPGA design
3 The implementation of the demo bundle
3.1 Overview
3.2 File outline
3.3 Generating the bitstream file with Vivado
3.4 Setting up AMD’s PCIe IP core
3.5 Generating the bit file with the ISE suite
3.6 Loading the bitfile
4 Modifications
4.1 Integration with custom logic
4.2 Inclusion in a custom project
4.3 Using other boards
4.3.1 General
4.3.2 Using Xillybus for PCIe
4.3.3 Working with Spartan-6 PCIe boards
4.3.4 Working with Virtex-6 PCIe boards
4.3.5 Working with Virtex-5 PCIe boards
4.3.6 Working with Kintex-7, Virtex-7 and Artix-7 boards (PCIe)
4.3.7 Working with Ultrascale and Ultrascale+ boards (PCIe)
4.3.8 Working with Versal ACAP boards (PCIe)
4.3.9 Working with XillyUSB
4.4 PRSNT pins for indicating the number of PCIe lanes
4.5 Changing the number of PCIe lanes and/or link speed
4.5.1 Introduction
4.5.2 The work procedure
4.5.3 Has the PIPE frequency changed?
4.5.4 Adapting the timing constraints
4.5.5 Updating the PIPE clock module
4.6 Changing the FPGA part number
5 Troubleshooting
5.1 Errors during implementation
5.2 PCIe Hardware problems
