1 Introduction
Xillybus is a DMA-based end-to-end solution for data transport between an FPGA and a host that runs Linux or Microsoft Windows. It offers a simple and intuitive interface to the designer of the FPGA logic as well as to the programmer of the software.
As shown above, the application logic on the FPGA only needs to interact with standard FIFOs.
For example, writing data to the lower FIFO in the diagram makes the Xillybus IP core sense that data is available for transmission in the FIFO’s other end. Soon, the IP core reads the data from the FIFO and sends it to the host, making it readable by the userspace software. The data transport mechanism is transparent to the application logic in the FPGA, which merely interacts with the FIFO.
On its other side, the Xillybus IP core implements the data flow utilizing PCI Express’ Transport Layer level, generating and receiving TLP packets. For the lower layers, it relies on AMD’s official PCIe core, which is part of the development tools, and requires no additional license (even when using the WebPACK edition).
The application on the computer interacts with device files that behave like named pipes. The Xillybus IP core and driver transport data efficiently and intuitively between the FIFOs in the FPGAs and their related device files on the host.
With XillyUSB, an MGT transceiver is used to implement an USB 3.0 interface, which is used for data transport instead of the PCIe interface mentioned above.
The IP core is built instantly per customer’s spec, using an online web application. The number of streams, their direction and other attributes are defined by customer to achieve an optimal balance between bandwidth performance, synchronization, and simplicity of design. After going through the preparation steps with the demo bundle, as described in this guide, it’s recommended to build and download your custom IP core at https://xillybus.com/custom-ip-factory.
This guide explains how to rapidly set up the FPGA with a Xillybus IP core, which can be attached to user-supplied data sources and data consumers, for real application scenario testing. The IP core is included in a demo bundle, which can be downloaded at the website.
Despite its name, the demo bundle is not a demonstration kit, but a fully functional starter design, which can perform useful tasks as is.
For those who are curious, a brief explanation on how Xillybus is implemented can be found in Appendix A of either Xillybus host application programming guide for Linux or Xillybus host application programming guide for Windows.