2 Prerequisites
2.1 Hardware
The Xillybus FPGA demo bundle is packaged to work with several boards and devices, as listed on the download pages (see section 2.2 below).
Owners of other boards may run a demo bundle on their own hardware after making the necessary changes in pin placements and verifying that the MGT’s reference clock is handled properly. This should be straightforward to any fairly experienced FPGA engineer. More about this in section 4.3.
2.2 FPGA project
The Xillybus demo bundle is available for download at Xillybus site’s download pages. For the PCIe-based cores:
https://xillybus.com/pcie-download
And for XillyUSB:
https://xillybus.com/usb-download
The demo bundle includes a specific configuration of the Xillybus IP core, which is intended for simple tests. Therefore, it has a relatively poor performance for certain applications.
Custom IP cores can be configured, automatically built and downloaded using the IP Core Factory web application. Please visit https://xillybus.com/custom-ip-factory for using this tool.
Any downloaded bundle, including the Xillybus IP core, is free for use, as long as this use reasonably matches the term “evaluation”. This includes incorporating the core in end-user designs, running real-life data and field testing. There is no limitation on how the core is used, as long as the sole purpose of this use is to evaluate its capabilities and fitness for a certain application.
2.3 Development software
The recommended tool for the implementation of Xillybus’ demo bundle (as well as other designs involving Xillybus) is listed below, depending on the FPGA’s family.
Xillybus for PCIe:
As of today, it’s almost certain that the Vivado version that is installed on your computer is suitable for working with Xillybus for PCIe. Nevertheless, these are the requirements in more detail:
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When using Virtex-5 FPGAs, the Xilinx ISE 13.1 version is preferred, see paragraph 4.3.5.
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For Spartan-6 and Virtex-6, use Xilinx ISE 13.2 and later.
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For Kintex-7 and Virtex-7 with Gen2 interface (all Virtex-7 that aren’t XT/HT, and 485T too), Vivado 2014.1 and later is the preferred tool. Among the ISE revisions, version 14.2 and later is recommended.
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For Virtex-7 with Gen3 interface (XT/HT except 485T), Vivado 2014.1 and later is preferred. If ISE is chosen, revision 14.6 and later is required.
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For Artix-7, Vivado 2014.1 and later should be used. ISE 14.6 and later is fine as well.
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For Kintex / Virtex Ultrascale, Vivado 2015.2 and later should be used. No ISE revision supports these devices.
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Ultrascale+ FPGAs require Vivado 2017.3 and later.
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Versal APAC FPGAs require Vivado 2021.2 and later.
XillyUSB:
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For all FPGAs except Ultrascale+, Vivado 2015.2 and later should be used.
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For Ultrascale+, Vivado 2018.3 and later should be used.
This software can be downloaded directly from AMD’s website (https://www.amd.com).
Any of this software’s editions is suitable. If the FPGA is covered by the WebPACK Edition, this edition may be the preferred choice, as it can be downloaded and used with no license fee for an unlimited time.
The implementation of Xillybus relies on some IP cores that are supplied by AMD. All software editions cover these IP cores, without any need for additional licensing.
2.4 Experience with FPGA design
When the design is intended for a board that appears in the list of demo bundles, no previous experience with FPGA design is necessary to have the demo bundle working on the FPGA. When other boards are used, it’s required to have some knowledge with using AMD’s tools, in particular defining pin placements and clocks.
To make the most of the demo bundle, a good understanding of logic design techniques, as well as mastering an HDL language (Verilog or VHDL) are necessary. Nevertheless, the Xillybus demo bundle is a good starting point for learning these, as it presents a simple starter design to experiment with.