1 Introduction
2 Synchronous streams vs. asynchronous streams
2.1 Overview
2.2 Motivation for asynchronous streams
2.3 Streams from FPGA to host
2.4 Streams from host to FPGA
2.5 Uncertainty vs. latency
3 I/O programming practices
3.1 Overview
3.2 Guidelines for reading data
3.3 Guidelines for writing data
3.4 Performing flush on asynchronous downstreams
3.5 Using Microsoft’s native API
3.6 Monitoring the amount of data in driver’s buffers
3.7 XillyUSB: The need to monitor the quality of the physical data link
4 Continuous I/O at high rate
4.1 The basics
4.2 Large driver’s buffers
4.3 RAM buffers in user space
4.4 Why not just Windows pipes?
4.5 Overview of the fifo.c demo application
4.6 fifo.c modification notes
4.7 RAM FIFO functions
4.7.1 fifo_init()
4.7.2 fifo_destroy()
4.7.3 fifo_request_drain()
4.7.4 fifo_drained()
4.7.5 fifo_request_write()
4.7.6 fifo_wrote()
4.7.7 fifo_done()
4.7.8 The FIFO_BACKOFF define variable
5 Cyclic frame buffers
5.1 Introduction
5.2 Adapting the FIFO example code
5.3 Dropping and repeating frames
6 Specific programming techniques
6.1 Seekable streams
6.2 Synchronizing streams in both directions
6.3 Packet communication
6.4 Emulating hardware interrupts
6.5 Coprocessing / Hardware acceleration
7 Hibernation
A Internals: How streams are implemented
A.1 Introduction
A.2 “Classic” DMA vs. Xillybus
A.3 FPGA to host (upstream)
A.3.1 Overview
A.3.2 Stage #1: Application logic to intermediate FIFO
A.3.3 Stage #2: Intermediate FIFO to DMA buffer
A.3.4 Stage #3: DMA buffer to user software application
A.3.5 Conditions for handing over partially filled buffers
A.3.6 Examples
A.3.7 Practical conclusions
A.4 Host to FPGA (downstream)
A.4.1 Overview
A.4.2 Stage #1: User software application to DMA buffer
A.4.3 Stage #2: DMA buffer to Intermediate FIFO
A.4.4 Stage #3: Intermediate FIFO to application logic
A.4.5 An example
A.4.6 Practical conclusions
