5 Troubleshooting
5.1 Errors during implementation
Slight differences between releases of AMD’s tools sometimes result in failures to run the implementation for creating a bitfile.
If the problem isn’t solved fairly quickly, please seek assistance through the email address given at Xillybus’ web site. Please attach the output log of the process that failed, in particular around the first error reported by the tool. Also, if custom changes were made in the design (i.e. diversion from the demo bundle) please detail these changes. Also please state which version of Vivado (or ISE) was used.
5.2 PCIe Hardware problems
Normally, the PCIe card is detected properly by the host’s BIOS and/or operating system, and the host’s driver launches successfully.
On most PC computers, the BIOS briefly displays a list of detected peripherals early in the boot process. When the Xillybus interface is detected successfully, a peripheral with vendor ID 10EE and device ID EBEB appears on the list.
As for the operating system’s detection of the card, please refer to one of these two documents, whichever applies:
The failure to detect the card (or a failure in the computer’s boot process) is not related to the Xillybus IP core, which relies on AMD’s PCIe IP core for interfacing with the bus.
At first, it’s recommended to verify the following:
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The bitstream was already loaded into the FPGA when the computer was powered on (or soon enough after it was powered on, in terms of the PCI-SIG specification).
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The pinouts of the PCIe wires, including the reference clock are correct (this can be verified in the placement report).
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The board supplies the correct reference clock to the FPGA.
If the problem isn’t spotted immediately, it’s recommended to attempt the sample project for PCIe that came with the board. This may reveal wrong jumper settings and possibly defective hardware.
If the card is detected with this sample, but not with Xillybus, it may be helpful to compare the pinouts of the two designs. If they are equal, the next step is comparing the attributes of the AMD’s PCIe cores by invoking the IP GUI for each (double-clicking the XCI / XCO element in the Project Manager with each of the projects open).
The following configuration elements may need adjustment:
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The frequency of the reference clock (may appear as “Interface Frequency” in the GUI).
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The base class and sub class (not likely, but some relatively old PC computers have failed the boot process if the class was considered unknown).
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Any other attribute that is configured differently, except for the base address register settings, vendor ID, device ID and interrupt settings, which should not be altered.
If the problem remains, please seek assistance through the email address given at Xillybus’ web site.