While Xillybus' main focus is data transport over PCIe, this is not always the optimal solution for certain designs. In particular, USB is often preferred for hardware that is hotpluggable and/or external to the computer.

Xillybus over USB is in its final design stages, and is scheduled for release in the upcoming months. The API on the FPGA side will be exactly the same as the current IP cores, with a plain FIFO interaction. This will allow a smooth transition from FPGA designs based upon Xillybus over PCIe to Xillybus over USB.

Some implementation details are yet to be established, however the IP core will cover only USB 3.0, without a fallback option to USB 2.0. This means that the host's port must be USB 3.0 compliant, or no communication takes place at all.

The host API is planned to remain the same as well, posssibly with slight differences.

Comments and other inquiries on this matter are welcome.