1 Introduction
The Xillybus Block Design Flow is an alternative to the Verilog / VHDL design flow, and is intended for those not comfortable with modifying and designing with logic-related HDL languages. Its primary purpose is to allow designers with no FPGA background an access to coprocessing / acceleration capabilities without the need to acquire FPGA-related skills. Among others, it’s intended as a simple means to exchange data between logic generated by AMD’s Vivado High Level Synthesis (HLS) and a computer or embedded platform running Linux or Microsoft Windows.
The Block Design Flow diverts from Xillybus’ main concept of communicating with the Xillybus IP core through FPGA FIFOs. Instead, user application logic connects directly to the Xillybus IP block through AXI Stream interfaces. This simplifies the work considerably, but requires awareness of the difference, in particular that when Xillybus’ documentation mentions FIFOs in the FPGA, this is irrelevant to the Block Design Flow: Instead of each FIFO, there is simple wire in the Block Design’s GUI.
Xillybus’ Block Design Flow should not be confused with the block design diagrams used for setting up a Zynq processor environment or otherwise connecting between logic blocks: Such block designs, if applied, are unrelated, and may coexist regardless of the method chosen for connecting Xillybus’ IP core with application logic.
Xillybus allows the designer to focus on productive, application related work by:
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Supplying a working starter project, which is ready for compilation into FPGA bitstream as is. This project sets up a simple and intuitive data exchange between the FPGA and the computer host by virtue of Xillybus’ IP core,
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supplying a sample High Level Synthesis (HLS) project for demonstrating logic design with C/C++, with the key elements explained in this guide (see section 6),
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allowing a very simple integration of IP blocks into the FPGA design, using Vivado’s block design tool
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supplying drivers for Linux and Windows that offer a simple programming interface on the host,
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offering a web tool which automatically creates custom Xillybus IP cores consisting of data streams that are configured specifically for a given project.
As the Block Design Flow relies on the block design tool of AMD’s Vivado, it’s limited to the FPGAs covered by this tool. Hence only AMD’s series-7 FPGAs and later (including Ultrascale devices) are supported.
Despite the ease of use of the Block Design Flow, it gives access only to a subset of Xillybus’ features, and is therefore not recommended for those familiar with FPGA design based upon Verilog or VHDL. However for certain applications, e.g. IP core or HLS-based hardware acceleration / coprocessing, the impact of the difference in Xillybus’ features is negligible.
The Block Design Flow is not supported by XillyUSB.