5 Applying a custom Xillybus IP core
A web application allows users to configure and download custom Xillybus IP cores, choosing the number of streams as well their attributes directly on Xillybus’ website. The specially generated custom IP core is then downloaded from the site, typically a few minutes later.
In order to generate and download a custom IP core, please visit the IP Core Factory at Xillybus’ website. The process is fairly straightforward, and if necessary, The guide to defining a custom Xillybus IP core supplies complimentary information.
IMPORTANT:
Seekable streams (with “address/data” interface) are invisible in the Block Design Flow, as the AXI Stream connections can’t support
the address wires. Having such streams in a core is fairly harmless, but causes a slight waste in FPGA logic resources, and a possible
confusion as they do appear on the host side, but not in the block design.
Once the custom IP core is defined, generate and download its bundle.
The instructions in the custom IP core bundle’s README file relate to the Verilog / VHDL design flow and should be disregarded. Instead, the following steps should be taken:
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Create a new directory for the custom IP core’s files. This directory’s absolute path must remain fixed throughout the use of this custom IP core, so it’s recommended to put it where it won’t be deleted accidentally.
Unzip the downloaded custom IP core bundle into this directory.
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Open the block design in Vivado.
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Save the block design’s view as a pdf file for reference: Right-click somewhere in the block design’s area, and choose “Save as pdf file...”.
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Pick “Run Tcl Script...” under the Tools menu (on the main menu bar). Navigate to the directory to which the custom IP core bundle was unzipped, and enter the xillybus_block subdirectory. Choose insertcore.tcl.
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The script will replace the existing Xillybus IP Core with the custom IP core, and also attempt to reconnect the wiring that is not related to the application. The objects may also move in the block design diagram due to an automatic reorganization.
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Connect the application logic’s AXI Stream interfaces to the updated Xillybus IP core.
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Compare with the pdf file that was created before running the script, and correct as necessary.
None of the application logic related connections are reconnected, and other connections may be missing as well.
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Verify that the captions below and under Xillybus IP Core’s block match the name of the new IP core.
Note that the script finds blocks, ports and interfaces by their names. It may therefore fail partially (and silently) in restoring connections if these names have been changed by the user.
From this point, the implementation of the project can be done as before. Xillybus’ driver for the host (Linux and Windows alike) works with the custom IP core as well, since it detects the new IP core’s configuration automatically.
Hence there’s no need to install anything on the host following the replacement with a custom IP core.
For reference, these are the steps of execution of the insertcore.tcl script:
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Add the directory of the custom IP core to the list of IP Core repositories in Vivado’s IP Catalog and force a rescan of the repositories, so the new custom IP Core is discovered and added to the Catalog
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Remove the previous Xillybus IP from the block design, if such is present
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Add the custom IP core to the design, and upgrade its version if necessary
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Attempt to reconnect wires going to the hierarchy above, as well as the wires to stream_clk_gen’s block, by looking up a list of names, and interconnecting all ports having these names, if present.
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On Zynq only: Set the bus address of the Xillybus IP core to its default values (a 4 kB segment starting at 0x50000000)
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Reset the synthesis run of the project, so the next implementation reflects the changes made.