1 Introduction
1.1 General
1.2 Obtaining Xillybus Lite
2 Usage
2.1 Sample design
2.2 Interface with Host application
2.3 Interface with logic design
2.3.1 Register related signals
2.3.2 Module hierarchy
2.3.3 32-bit aligned register access
2.3.4 Unaligned register access
2.4 Interrupts
3 Xillybus Lite on projects not using Xillinux
3.1 Applying the IP core
3.2 Modifying the device tree
3.3 Compilation of the Linux driver
3.4 Installing the driver
3.5 Loading and unloading the driver
