1 Introduction
1.1 General
Xillybus Lite is a simple kit for easy access of registers in the logic fabric (PL) by a user space program running under Linux. It presents an illusion of a bare-metal environment to the software, and a trivial interface of address, data and read/write-enable signals to the logic design.
Using this kit frees the development team from dealing with the AXI bus interface as well as Linux kernel programming, and allows a straightforward memory-like control of the peripheral without the need for any knowledge on the the operating system or the bus protocol.
The kit consists of an IP core and a Linux driver. These are included in the Xillinux distribution for the Zedboard (versions 1.1 and up), and are also available for download separately for inclusion in projects.
Xillybus Lite does not involve any DMA functionality. The maximal data rate is around 28 MB/s (7 Million 32-bit accesses of reads or write per second, with the processor clock at 666 MHz).
The Xillybus Lite IP core is released for any use at no cost. In particular, it may be downloaded, copied and included in binaries used and sold for commercial purposes with no limitation and without any additional consent nor specific licensing.
The Xillybus Lite driver for Linux is released under GPLv2, which makes it free for distribution under the same terms as the Linux kernel itself.
1.2 Obtaining Xillybus Lite
For learning about Xillybus Lite and trying it out, it’s recommended to download and install Xillinux (version 1.1 and above).
The distribution has everything set up for trying out Xillybus Lite on sample logic that can be easily modified in xillydemo.v/vhd. The Linux side has the driver already installed and a couple of sample programs to start off with.
Xillinux can be downloaded at https://xillybus.com/xillinux
To verify that an existing installation is recent enough, the following check can be run at the shell prompt on Xillinux:
# uname -r 3.3.0-xillinux-1.1+
The suffix (“1.1” in the example above) shows the Xillinux version (which is OK in this case).
Xillybus Lite can be included in any Zynq-7000 design, regardless of Xillinux. This requires the inclusion of the IP core in the XPS project, some wiring, compilation and installation of the driver, as described in section 3.
The Xillybus Lite bundle can be downloaded at https://xillybus.com/xillybus-lite