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2 Prerequisites

2.1 Hardware

Xillybus relies on the Altera’s hardware IP block for PCI Express, and is hence available for any Altera device having this component. Among the FPGA families supported:

  • Arria II GX/GZ

  • Cyclone IV GX

  • HardCopy IV GX

  • Stratix IV GX

  • Arria V GX/GT/SX/ST

  • Cyclone V GX/GT/SX/ST

  • Stratix V GS/GX/GT

  • Arria 10 GX/GT/SX

  • Cyclone 10 GX

  • Stratix 10 with H-tile or L-tile

XillyUSB is supported only with Cyclone 10 GX (the LP family is not supported).

The Xillybus FPGA demo bundle is packaged to work with several boards and devices, as listed on the download pages (see section 2.2 below).

Owners of other boards may run a demo bundle on their own hardware after making the necessary changes in pin placements and verifying that the MGT’s reference clock is handled properly. This should be straightforward to any fairly experienced FPGA engineer. More about this in section 4.4.

2.2 FPGA project

The Xillybus demo bundle is available for download at Xillybus site’s download pages. For the PCIe-based cores:

https://xillybus.com/pcie-download

And for XillyUSB:

https://xillybus.com/usb-download

The demo bundle includes a specific configuration of the Xillybus IP core, which is intended for simple tests. Therefore, it has a relatively poor performance for certain applications.

Custom IP cores can be configured, automatically built and downloaded using the IP Core Factory web application. Please visit https://xillybus.com/custom-ip-factory for using this tool.

Any downloaded bundle, including the Xillybus IP core, is free for use, as long as this use reasonably matches the term “evaluation”. This includes incorporating the core in end-user designs, running real-life data and field testing. There is no limitation on how the core is used, as long as the sole purpose of this use is to evaluate its capabilities and fitness for a certain application.

2.3 Development software

The recommended tool for the implementation of Xillybus’ demo bundle (as well as other designs involving Xillybus) is listed below, depending on the FPGA’s family.

Xillybus for PCIe:

  • For FPGAs of series-IV and Arria II: Quartus 12.0 and later.

  • For Arria 10 and Cyclone 10: Quartus Prime 17.1 and later. Both the Standard and Pro editions are supported.

  • For Stratix 10: Quartus Pro 19.2 and later.

  • All other FPGA families: Quartus II, version 15.0 and later.

XillyUSB:

  • For Cyclone 10: Quartus Pro 17.1 and later should be used.

This software can be downloaded directly from Altera’s website (https://www.altera.com).

Note that Web / Lite Editions of Quartus, which are available at no cost, support several FPGA families, in particular Cyclone devices.

The implementation of Xillybus relies on some IP cores that are supplied by Quartus. All editions of Quartus cover these IP cores, without any need for additional licensing.

2.4 Experience with FPGA design

When the design is intended for a board that appears in the list of demo bundles, no previous experience with FPGA design is necessary to have the demo bundle working on the FPGA. When other boards are used, it’s required to have some knowledge with using Altera’s tools, in particular defining pin placements and clocks.

To make the most of the demo bundle, a good understanding of logic design techniques, as well as mastering an HDL language (Verilog or VHDL) are necessary. Nevertheless, the Xillybus demo bundle is a good starting point for learning these, as it presents a simple starter design to experiment with.